September 29, 2006
EE Conference Room 1312 Mudd
Hosted by: Integrated System Laboratory
Speaker: Dr. Scott Reynolds, IBM Thomas J. Watson Research Center
A 0.13-um SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject LNA, RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, PLL, and frequency tripler. It achieves a 6-dB NF, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a PA, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12 dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s and 10 m has been demonstrated. Wireless transmission of un-compressed high-definition digital video at 2 Gb/s has also recently been achieved.