Circuits and Architectures for Power-Efficient High-Speed Electrical I/O<-- Return to the list
Abstract: Advances in digital computing capabilities create higher demands for serial data transmission. Sustaining these bandwidth demands requires innovations on several fronts. Future packaging technologies must enable ultra-dense chip-to-chip interconnects. This in turn creates a need for compact, power-efficient I/O with equalization capable of supporting multi-Gb/s communication over these interconnects. In this talk, solutions to enable future electrical I/O bandwidth demands will be presented. After a brief overview of equalization techniques, design examples of equalizing receivers in 45nm SOI CMOS technologies will be shown, focusing on low-power circuits and architectures. Additionally, a compact 8x10-Gb/s I/O subsystem mounted to a silicon interposer via 50mm pitch "micro-C4" bumps will be described. The I/O includes a DFE-IIR equalizer in the receiver tailored for lossy silicon carrier interconnects, and bus-level redundancy that enables periodic recalibration of each serial link in a round-robin fashion. This work demonstrates the potential of silicon packaging technologies for achieving high bandwidth chip-to-chip communication by sending multi-Gb/s data over a large number of parallel interconnects, paving the way for increased module bandwidth for high-performance computing systems.
Speaker Bio: Timothy (Tod) Dickson received the B.S. and M.Eng. degrees in Electrical Engineering from the University of Florida, and the Ph.D. degree from the University of Toronto. Since 2006, he has been with the IBM T.J. Watson Research Center in Yorktown Heights, NY, where he is currently a Research Staff Member. His research focuses on the design of low-power multi-Gb/s serial I/O transceivers. He is also an Adjunct Assistant Professor at Columbia University in New York City, where he teaches graduate-level courses in analog and mixed-signal circuits and systems. Dr. Dickson has been a recipient or co-recipient of several best paper awards, including the Best Paper Award for the 2009 IEEE Journal of Solid-State Circuits, the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the Best Student Paper Award at the 2004 Symposium on VLSI Circuits, and the Best Paper Award at the 2011 IEEE Conference on Electrical Performance of Electronic Packaging and Systems. He served as a member of the Technical Programming Committee of the IEEE Compound Semiconductor Integrated Circuit Symposium from 2007-2009, and was a guest editor of the October 2010 issue of the IEEE Journal of Solid-State Circuits.