Beyond CMOS Scaling: What's a Circuit Designer to Do?
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Date: 12-07-2012
Start Time:
1:00pm
End Time: 3:00pm
Speaker: Dr. Leland Chang
From:
IBM T.J. Watson Research Center
Location: 633 Mudd
Hosted by:
Columbia Integrated Systems Laboratory
Abstract: As decades of sustained CMOS technology scaling begins to slow, the silicon microelectronics industry must look to new, innovative techniques to improve performance and power efficiency. To build the next generation of computing systems, today's circuit designer must understand not only the possibilities of new, emerging technologies, but also how system architecture can be changed to meet the evolving needs of the end-user. Such blurring of the boundaries between devices, circuits, and systems as well as those between digital, mixed-signal, and analog circuits will be essential in future research work. Exemplary directions will be discussed to show that there is much exciting work to be done in the circuits field beyond CMOS scaling and its traditional focus on digital logic performance. In computing systems as we know them today, there is yet significant room to improve the efficiency of system subcomponents such as embedded memory and power delivery/management. Going forward, there may be even more room to develop new circuits that are radically more efficient by invoking architectural changes in parallelism, accelerators, and heterogeneous systems to serve future applications needs.
Biography: Leland Chang received the BS, MS, and PhD degrees in EECS from UC Berkeley, where his work focused on early demonstration of the FinFET transistor structure for CMOS scaling. He joined IBM in 2003 and soon realized that embedded memory was just as important as (if not more so than) logic computation. Masquerading as an array designer, he demonstrated 6T-SRAM cells scaled to record sizes, 8T-SRAM for voltage scalability, and double-pumped register files for density and fast latency. More recently, he has worked to improve his analog design skills by developing on-chip voltage regulators based on new integrated passives while keeping his digital design skills in check while studying low voltage applications. Day to day, he splits time between managing a technology group that dabbles all too often in circuits and systems, pursuing the never-ending quest for power efficiency in high performance systems, and keeping pace with the ISSCC technical program committee.