Power Reduction in High Speed Flash Analog-to-Digital Converters using Distortion Correction
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Date: 05-25-2007
Start Time:
2:00pm
End Time: 3:00pm
Speaker: Shanthi Pavan
From:
Indian Institute of Technology-Madras
Location: 414 CEPSR
Hosted by:
Columbia Integrated System Laboratory
We present a flash ADC design technique that compensates for static nonlinearity of the up-front sample and hold circuit, so that high speed and high linearity can be obtained at the same time. This enables the use of a significantly larger input signal swing than would otherwise be possible, translating eventually into reduced power dissipation. The proposed technique functions in synergy with a new background comparator offset correction scheme. We demonstrate the efficacy of our techniques with measurement results from a 160 Msps 6-bit flash converter designed in a 0.35-$\mu\rm{m}$ CMOS process. The ADC consumes 50~mW from a 3.3~V power supply and has an ENOB of 5.3 bits at Nyquist.