ESD for advanced CMOS nodes
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Date: 04-07-2006
Start Time:
2:00pm
End Time: 3:00pm
Speaker: Benjamin Van Camp
From:
Sarnoff Europe
Location: EE Conference Room 1312 S.W. Mudd
Hosted by:
Integrated System Laboratory
Due to the continuous scaling of the CMOS technology, Electro Static Discharge (ESD) protection design is ever more challenging. Ultra thin gate oxides and sensitive output drivers drastically reduce the available voltage margin for the traditional protection approaches. After a basic introduction on on-chip ESD protection, the tutorial presents an overview of the different protection approaches and their applicability for the emerging IC's and systems in advanced technology nodes.