Nanometer-Scale Self Assembly in Semiconductor Microelectronics
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Date: 03-01-2006
Start Time:
4:00pm
End Time: 5:00pm
Speaker: Dr. Charles Black
From:
IBM T. J. Watson Research Center
Location: Interschool Lab, 7th floor, Schapiro/CEPSR
Hosted by:
Center for Integrated Science
Abstract:
The challenge of defining semiconductor integrated circuit elements at sub-100 nanometer dimensions has created opportunities for alternative patterning approaches. One attractive non-traditional approach utilizes the phenomenon of self assembly. Under suitable conditions, certain materials self organize into patterns offering promise for enabling further advances in semiconductor microelectronics. Diblock copolymers are particularly attractive for this application because like photoresist materials used for lithography, they can act as sacrificial templates for patterning integrated circuit elements. We have successfully integrated a polymer self assembly process into our 200mm semiconductor fabrication facility. Self assembly has applications in both today's and future microelectronics, and materials integration is the critical first step for adoption into high-performance semiconductor technology. We will describe key applications of self assembly in high-performance semiconductor device fabrication, including its use in on-chip decoupling capacitors, nanocrystal FLASH memories, and multi-nanowire field-effect transistors. The discussion will highlight both the promise and versatility of this technique, as well as some limitations and challenges still to be addressed.