Templated Growth of Semiconductor Nanostructures through Block Copolymer Lithography
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Date: 04-28-2006
Start Time:
2:00pm
End Time: 3:00pm
Speaker: Azar Alizadeh
From:
GE Global Research
Location: Interschool Lab, 7th floor, Schapiro/CEPSR
Hosted by:
Center for Integrated Science
Abstract:
III-V semiconductor nanostructures have the potential to revolutionize
a variety of technologies such as optoelectronics, field emission and
high temperature sensing. Presently, it appears that the selective area
or templated growth method is perhaps one of the more promising avenues
for fabrication of tailored and highly confined semiconductor
nanostructures. Templated growth of semiconductor nanostructures, which
involves epitaxial growth through a selective mask, allows for precise
control over quantum dot size, shape, spacing and uniformity, and could
potentially mitigate the nonradiative defects associated with the
direct writing techniques [1,2]. Selective growth of III-V
semiconductor structures, particularly gallium arsenide and gallium
nitride, using a dielectric mask with micron size openings has been
extensively reported in the literature. In comparison, there appears to
be only few reports on the selective growth of III-V nano-structures
inside sub-100 nm SiO2 windows. Here, we report on the templated growth
of III/V nanostructures inside sub-20 nm SiO2 windows using molecular
beam epitaxy (MBE).
This work has been accomplished in collaboration with K. Conway, L.
Denault, D. Hays, C. Keimel R. Klinger, S. Krishna, K. Krishnan, F.
Sharifi, A. Stintz and S.T. Taylor.