October 24, 2014
EE Conference Room
Speaker: Mike Shuo-Wei Chen, Professor, University of Souther California
The trend of modern electronic systems in both wireless and wireline applications demands
increasing bandwidth, dynamic range, and reconfigurability but low power and cost. On the
other hand, the technology scaling is slowing down its pace and incurs significant cost
particularly for analog designs. Those factors have driven the mixed-signal design community
to pursue new circuit architectures towards unprecedented performance, power efficiency and
flexibility. In this talk, we will examine several such attempts in ADC, DAC, and PLL designs
recently demonstrated by our group members. The initial silicon prototypes in 65nm CMOS
achieve encouraging power efficiency and performance in comparison with the state of the
arts, which tout the potential for many future extensions.
Mike Shuo-Wei Chen received the B.S. degree from National Taiwan University in 1998, and the
M.S. and Ph.D. degree from the University of California, Berkeley in 2002 and 2006, all in
Electrical Engineering. Since 2006, he has been working on mixed-signal and RF circuits for
various wireless standards at Atheros communications (now Qualcomm-Atheros). He joined EE
department at University of Southern California since 2011. His research group is having fun
with exploring the limit of analog mixed-signal, RF ICs, Bio-inspired electronics, and signal
processing techniques for circuits and systems.
Dr. Chen achieved an honourable mention in the Asian Paciﬁc Mathematics Olympiad, 1994. He
was the recipient of NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty
Award (YFA) in 2014, UC Regents’ Fellowship at Berkeley in 2000 and Analog Devices
Outstanding Student Award for recognition in IC design in 2006.
Hosted by Harish Krishnaswamy.