- Review of MOS design physics and CMOS scaling trends
- BSIM device models, emerging technology issues affecting
- (e. g. subthreshold and gate leakage)
- Static CMOS
- Sizing for speed, review of method of logical effort
- Interconnect analysis
- RC and RLC on-chip interconnect analysis.
- Explicit moment-matching techniques.
- Implicit moment-matching techniques based on Krylov-subspace
- model-order reduction.
- Other non-clocked logic styles
- Differential static CMOS style (i. e. DCVS)
- Current-mode logic
- Pass transistor logic
- Clocked storage elements: latches and flip-flops
- pass-transistor and tri-state inverter latch
- TSPC latches
- sense-amplifier based latches
- Clocked logic families
- Domino, delay-reset domino
- Self-resetting domino
- Clocking styles, single phase and multiphase clocking
- with clocked and unclocked logic families. Cycle stealing
- Self-timed design with clocked and non-clocked logic.
- Low-power design techniques
- "optimal" energy-delay product as a function of Vdd/Vth
- on-chip voltage regulation and well biasing
- use of multi-Vts for leakage reduction
- clock gating
- adiabatic logic
- Design considerations for SOI technology.
- SRAM design
- self-resetting SRAM design techniques, wave-pipelining
- sense amps, replica bit lines
- DRAM design
- Power supply distribution.
- Low-skew clock distribution techniques: clock trees and
- PLL/DLL design. Basic building blocks: phase detector, charge
pump, delay lines, VCO.
- Introduction to Verilog A
- I/O circuitry
- Low-voltage interface standards (e. g. SSTL and GTL)
- ESD protection
- Driver and receiver design