ELEN E4321

• Introduction to VLSI Design
  
  
• History of integrated circuits and technology scaling
• Levels of abstraction and the complexity of design
• Challenges of VLSI design: power, timing, area, noise, testability, reliability and yield
• CAD tools: simulation, layout, synthesis, test, data management
• Semiconductor device physics and MOS modelling (2 Lectures)
• pn junction models
• MOS device models
• MOS capacitors
• Short-channel effects and velocity saturation
• Introduction to BSIM3v3 device models
• Scaling of MOS circuits
• Fabrication and layout
• VLSI fabrication technology
• Layout view
• Layout CAD tools, Cadence Virtuoso, and the TSMC 0.25 layers
• Design rules: resolution rules and alignment rules
• TSMC 0.25 design rules, and learning to read a design manual
• Stick diagrams, layout planning, and size estimation
• The CMOS inverter
• What makes a good logic gate?
• Voltage transfer characteristic (dc behavior)
• Switching behavior
• Noise margins and power dissipation
• Static and dynamic CMOS combinational logic gate, capacitance, and switch level modeling
• Transistor sizing in static CMOS, logical effort
• Pass-transistor logic, sizing issues in pass-transistor design
• Domino logic gates
• Rules of thumb for estimating load capacitance
• Simple delay models (RC) for CMOS gates
• Power consumption
• Switch-level simulation models
• Latches and clocking
• Flip-flops versus latches
• Set-up and hold tests
• Static and dynamic latch and flip-flop circuits
• Clock design and clock skew
• Pulse-mode clocking, two-phase clocking
• Static timing analysis
• Datapath functional units
• Adders
• Shifters
• Multipliers
• Control logic strategies
• PLAs
• Multi-level logic implementations
• Synthesis and place-and-route CAD
• MOS memories
• Register files
• SRAM
• DRAM
• Global interconnect modelling
• Capacitance, resistance, and inductance of interconnect
• Signal and power-supply integrity issues
• Electromigration
• RC interconnect modelling
• Driving large capacitive load, reducing RC delays
• Structured layout design
• Structured bitslice layout
• Standard-cell layout
• Chip layout and floorplanning
• Array layout
• Other implementation issues
• Design for testability
• Packaging technology
• I/O issues: ESD protection, boundary scan, inductance, synchronization