Microelectronic Test Structures for CMOS Technology

April 10, 2014
2:00-3:00pm
Location: 414 CEPSR
Speaker: Dr. Mark B. Ketchen, OcteVue

Abstract

In scientific investigation and in launching a manufacturing technology through its stages of research and development, test structures are used to facilitate characterization and control of key aspects of the integrated whole. With scaling to deep sub-µm dimensions, the cost and complexity of CMOS technologies continues to rise. Appropriately designed test structures add efficiency and reduce cost and time to market. Examples of innovative CMOS test structures and measurement techniques covering from DC to multi-GHz frequencies are described. Emphasis is placed on a methodology that bridges both upward in the hierarchy to complex circuitry and downward to the properties of the constituent components. The designs and concepts presented are based on the work originally done for IBM's microprocessor chip technologies.

Speaker Bio

Mark B. KetchenMark B. Ketchen is the sole proprietor of OcteVue, providing technical consulting services in microelectronic technologies. He earned his BS in Physics from MIT in 1970 followed by four years as a Naval Officer and completion of a Ph.D in Physics from UC Berkeley in 1977. He spent 36 years at IBM, holding a variety of positions in science and technology, ranging from individual investigator to serving as Director of IBM's international program in Physical Sciences. He was a pioneer in the design, fabrication and characterization of integrated DC SQUIDs, led design and test efforts in IBM's early attempt to build a superconducting computer, and has recently driven advances in qubits for quantum computing. He worked in silicon bipolar technology integration, ran the silicon fab line at IBM Research in the late 1980s, and worked on design and utilization of custom DC and high speed test structures for CMOS characterization and evaluation at the 180 nm through 32 nm technology nodes.

Dr. Ketchen has 43 issued or pending patents over 180 publications and is co-author of the book Microelectronic Test Structures for CMOS Technology published by Springer. He is a Life Fellow of the IEEE, a Life Fellow of the American Physical Society and a past recipient of the American Institute of Physics Prize for Industrial Applications of Physics and the IEEE Leeds award. He is a citizen of the US and Canada and holds a US Government security clearance.

Hosted by Mingoo Seok.


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