IEEE SSCS Distinguished Lecture: Digital Phase-Locked Loops Open Up New Avenues For Clock Generation in SoCs

October 2, 2009
Time: 11:00am-12:00pm
Interschool Lab, Shapiro/CEPSR Building, 7th Floor
Hosted by: Prof. Peter Kinget
Speaker: Krishnaswamy Nagaraj, , Distinguished Member of Technical Staff, Texas Instruments

This is an "IEEE SSCS Distinguished Lecture" organized by the New York EDS/SSCS Chapter and co-organized by the "Columbia Integrated Systems Lab".

Abstract

Phase lock loops (PLLs) are an indispensable part of today’s systems-on-chip (SOCs). They are used extensively for generating clocks for digital signal processing blocks, as well as carriers for RF receive/transmit blocks. Traditional implementations of PLLs have been analog in nature. With the trend towards system integration using digital CMOS technologies, a new class of PLLs, namely, Digital Phase Lock Loops (DPLLs) has emerged recently. DPLLs offer several advantages, including the elimination of passive components, flexibility and programmability and the possibility of applying sophisticated DSP techniques to improve performance and reduce power consumption. This talk will present an overview of recent developments in DPLL architectures and circuits.

 

Speaker Biography

Krishnaswamy Nagaraj is presently a Distinguished Member of Technical Staff with Texas Instruments in Dallas, where he is engaged in the development of low power, high performance circuits and systems in nanometer CMOS technologies. Previously, he was a Distinguished Member of Technical Staff at the Bell Laboratories in Murray Hill, New Jersey. He has served as an Associate Editor of the IEEE Transactions on Circuits and Systems Part II, IEEE Journal of Solid State Circuits and as the Editor-in-Chief of the IEEE Journal of Solid State Circuits. He was an Adjunct Associate Professor at the University of Pennsylvania from 1996 to 2003. He is a Fellow of the IEEE.

 

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