High-Speed IC Designs for Future Communication Systems

October 18, 2007
Time: 2:00pm-3:00pm
EE Conference Room 1312 S.W. Mudd
Hosted by: Columbia Integrated System Laboratory (CISL)
Speaker: Prof. Jri Lee, National Taiwan University

Abstract

Recent developments on wireless and wireline communications have pushed the operation freuqency toward tens of gigahertz. This talk presents novel high-speed techniques for different applications as well as their silicon realizations, comprising a 75-GHz PLL, a 20-Gb/s burst-mode CDR, and a 60-GHz RF front end. Future design trends for high-speed circuits are also included.

Speaker Biography

Jri Lee received the B.Sc. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan in 1995, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles (UCLA), both in 2003. His current research interests include high-speed wireless and wireline transceivers, phase-locked loops, and data converters. He has been an Assistant Professor in electrical engineering at National Taiwan University since 2004. Prior to that, he had military service for 2 years and worked in the industry/research institute for 3 years. Dr. Lee received the Beatrice Winner Award for Editorial Excellence at the 2007 ISSCC, and NTU Outstanding Teaching Award in 2006. He is currently serving in the technical program committees of International Solid-State Circuits Conference (ISSCC) and Asian Solid-State Circuits Conference (A-SSCC).


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