SEAS Department Website

Charles A. Zukowski joined the EE faculty in 1985. He is the author of the book The Bounding Approach to VLSI Circuit Simulation (Kluwer Academic, 1986), which explores topics circuit theory, mathematics, and software design. He is currently working on designing high-speed and low-energy digital ICs for communications networks. Examples include switches, buffers, packet error checkers, and time-division multiplexers. His current interests range from circuit architecture to software analysis tools, and he consults in the field of CMOS IC design. He is a recipient of a Presidential Young Investigator Award from the NSF in the field of CAD. He has also been active in the IEEE both as a reviewer and in the organization of conferences.

• Ph.D., MIT (1985)
• M.S.E.E., MIT (1982)
• B.S.E.E., MIT (1982)

• Design and analysis of digital VLSI circuits
• Circuit simulation
• Communication circuits
  
  

• Chairman, Electrical Engineering Department, Columbia University (July 2000– )
• Acting Chair of Electrical Engineering Department, Columbia University (June 1998–June 1999)
• Faculty / Various Consulting Electrical Engineering Department, Columbia University (September 1985– )
• Research Associate, MIT (Summer 1985)
• Teaching Assistant, MIT (Various 1980-85)  
• IBM T. J. Watson Research Center (Summers 1979–82)

S. Wang & C. Zukowski, "Energy Reduction from Using Selective Precharge in Two Different Logic Arrays," to appear at IEEE Midwest Symp. on Circuits & Systems, Aug. 2000.

N. Abassi & C. Zukowski, "Trading System Performance for Energy use in a VLSI Implementation of an Adaptive Equalizer," to appear at IEEE Midwest Symp. on Circuits & Systems, Aug. 2000.

S. H. Li & C. Zukowski, "Application of Dynamic Power Supply Scaling in a Low-energy ATM interface," IEEE Int. Symp. on Circuits and Systems (ISCAS 2000) Geneva, Switzerland, May 2000, pp. v745-v748.

A. Renshaw, J. Reibel, C. Zukowski, K. Penn, R. McClintock, & M. Friedman, "An Assessment of On-Line Engineering Design Problem Presentation Strategies, IEEE Trans. on Education, Vol. 43, No. 2, May 2000, pp. 83-91.

G. Dare & C. Zukowski, "Accuracy Management for Mixed-Mode Digital VLSI Simulation," Proc. of Tenth Great Lakes Symp. on VLSI, Mar. 2000, pp. 167-170.

G. Gristede, C. Zukowski, & A. Ruehli, "Measuring Error Propogation in Waveform Relaxation Algorithms," IEEE Trans. Circ. & Sys. I: Fund. Thy. & Appl., Vol. 46, No. 3, Mar. 1999, pp. 337-348.

C. Tretz, C. T. Chuang, L. Terman, M. Palella & C. Zukowski, "Performance Comparison of Differential Static CMOS Circuit Topologies in SOI Technology", 1998 International Conference on SOI, Oct. 1998, pp. 123-124.

G. Gristede, A. Ruehli, & C. Zukowski, "Convergence Properties of Waveform Relaxation Circuit Simulation Methods," IEEE Trans. on Circ. & Sys. I: Fund. Thy. & Appl., Vol. 45, No. 7, July 1998, pp. 726-738.

C. Tretz, C. T. Chuang, L. Terman, C. Anderson & C. Zukowski, "Metastability in SOI CMOS Latches", 1997 International Conference on SOI, Oct. 1997, pp. 162-163.

C. Zukowski, and S-Y. Wang, "Use of Selective Precharge for Low-Power on the Match lines of Content-Addressable Memories," IEEE Int. Workshop on Memory Tech., Design and Testing, Aug. 1997, pp. 64-68.

S. H. Li & C. Zukowski, "A Self-Timed CRC With Feedback Scheme," 40th Midwest Symp. on Circ. & Sys., Aug. 1997, pp. 1021-1025.

C. Zukowski & S-Y. Wang, "Use of Selective Precharge for Low-Power Content-Addressable Memories," 1997 IEEE International Symposium on Circuits and Systems, June 1997, pp. 1788-1791.

C. Zukowski, and S-Y. Wang, "Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge," 1997 7th Great Lakes Symp. on VLSI, Mar. 1997, pp. 83-87.

C. Tretz, S. Ranganathan & C. Zukowski, "Comparison of a Wide Range of Differential CMOS Logic Topologies", 1996 Midwest Symposium on Circuits and Systems, Aug. 1996, pp. 179-182.

C. Tretz & C. Zukowski, "Modeling of the Contribution of Spurious Transitions to Power Dissipation in Digital CMOS VLSI Circuits", 1996 Midwest Symposium on Circ. and Sys., Aug. 1996, pp. 317-320.

C. Tretz & C. Zukowski, "CMOS Transistor Sizing for Minimization of Energy-Delay Product," Proc. of 6th Great Lakes Symp. on VLSI, Mar. 1996, pp. 168-173.

H. Shi, C. Zukowski, & O. Wing, "VLSI Design Optimization of Input/Output-Buffered Broadband ATM Switches," Proc. of IEEE INFOCOM96, Mar. 1996, pp. 810-817.