A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer

May 30, 2014
Location: Mudd 825
Speaker: C. Patrick Yue, Professor, Hong Kong University of Science and Technology
Host: Peter Kinget


The rising demand for short-range optical links using 850-nm wavelength has generated strong interest in CMOS optoelectronic integrated circuits (OEICs). Compared to existing hybrid solutions employing off-chip GaAs-based avalanche photodetectors (PDs), single-chip OEICs with on-chip PDs can lower optical module assembly cost and eliminate the parasitic effects due to the bond-wire and ESD protection circuit at the receiver input. However, CMOS PDs have poor responsivity (<50 mA/W) under standard supply bias due to their shallow junction depth (~1 µm) relative to the 850-nm light absorption length in silicon (>15 µm). Moreover, typical CMOS PD bandwidth (BW) is <100 MHz limited by substantial junction capacitance and large carrier transit time in the substrate. By operating in avalanche mode, the responsivity and BW can be greatly enhanced but it requires a large bias voltage (>10 V). In general, equalization circuits are required for gain compensation to boost the data rate (DR) above 5 Gb/s. The stat-of-the-art performance demonstrated by a monolithic 850-nm optical receiver can achieve a maximum data rate of 12.5 Gb/s while consuming 4.72 pJ/bit.

This work presents a complete 850-nm optical receiver designed in a standard 1-V 65-nm CMOS process integrating the PD, transimpedance amplifier (TIA), continuous-time linear equalizer (CTLE) with adaptive self-controlled loop, limiting amplifier (LA), and dc offset cancellation (DOC) circuits to achieve a record performance at 18 Gb/s with 2.7 pJ/bit.

Speaker Bio

Prof. C. Patrick Yue is currently the Associate Provost for Knowledge Transfer (AP-KT) as well as a Professor in Electronic and Computer Engineering at the Hong Kong University of Science and Technology (HKUST). He is the founding Director of the Center for Industry Engagement and Internship in the School of Engineering at HKUST. His current research interests include high-speed optical communication transceiver system-on-a-chip (SoC), wireless power transfer and power management IC for biomedical implants, LED SoC microsystems for lighting, display, and visible light communication.

Based on his PhD work at Stanford University, in 1998, he co-founded Atheros Communications. He applied his expertise in CMOS RF transistor and passive component modeling to enable the deployment of the world's first 802.11a 5-GHz CMOS RF transceiver. In 2002, he joined anther Silicon Valley startup Aeluros to develop 10-Gbps CMOS serdes IC products for the optical-to-electrical modules based on the XAUI interface. Prof. Yue has held a consulting faculty position at Stanford and has taught at Carnegie Mellon University and University of California Santa Barbara before joining HKUST in 2011. Prof. Yue remains passionate about technology entrepreneurship and is an active advisor to a number of IC startups based in the US and mainland China.

He has contributed to more than 100 peer-reviewed technical papers and two book chapters. He holds 13 U.S. patents of which most are employed in IC products. He is the author of one of the all-time most cited paper in the IEEE Journal of Solid-State Circuits (with Google citation index over 1000). Dr. Yue was a co-recipient of the International Solid-State Circuits Conference Best Student Paper Award in 2003. He has served on the executive, organizing and technical committees of a number of international conferences including IEEE International Wireless Symposium, IEEE Radio-Frequency Integrated Circuits Symposium, IEEE Symposium on VLSI Circuits, Asian Solid-State Circuits Conference, International Symposium on VLSI-Design, Automation and Test, and IEEE International Symposium on Radio Frequency Integration Technology. He has been an Editor of the IEEE Electron Device Letters since 2011.

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